1. Field of the Invention
The invention relates generally to cleaning processes for microelectronic structures. More particularly, the invention relates to cleaning processes for microelectronic dielectric and metal structures.
2. Description of the Related Art
Microelectronic structures, and in particular semiconductor structures, are generally fabricated using successive layering processes that are intended to fabricate successive portions of a microelectronic structure over a microelectronic substrate, such as a semiconductor substrate. The fabrication of successive portions of a microelectronic structure over a microelectronic substrate may use any of several microelectronic fabrication processes. Non-limiting examples include ion implant processes, photolithographic processes, selective etch processes and selective deposition processes.
Common in the microelectronic fabrication art is the use of cleaning processes for cleaning microelectronic structures, such as semiconductor structures, at intermediate points in the fabrication of those microelectronic structures. Such cleaning processes are desirable insofar as such cleaning processes remove residues from microelectronic structure surfaces so that fully functional and reliable completed microelectronic structures may be fabricated from the residue laden partially completed microelectronic structures.
While effective and efficient cleaning processes are certainly desirable at any stage of microelectronic structure fabrication, effective and efficient cleaning processes are often particularly desirable within the context of microelectronic dielectric and metal structure fabrication, since ineffectively or inefficiently cleaned microelectronic dielectric and metal structures are often readily discernible through electrical measurements. Similarly, a particular dielectric and metal structure that may be desirably cleaned to provide a functional and reliable microelectronic structure is a dual damascene structure. A dual damascene structure includes a dual damascene aperture that in turn includes a via aperture contiguous with an overlying trench aperture within a dielectric layer. The dual damascene structure also includes a contiguous via and interconnect layer located and formed into the corresponding via aperture contiguous with the trench aperture within the dual damascene aperture.
Various cleaning processes having desirable properties are known for cleaning microelectronic structures within the microelectronic fabrication art.
For example, Nasher et al., in U.S. Pat. No. 6,465,358, teaches a method for cleaning a semiconductor structure that may include a dual damascene aperture. This particular method sequentially uses: (1) a buffered oxide etchant treatment; followed by (2) an amine based solution treatment.
In addition, Eissa et al., in U.S. Pat. No. 6,551,943, teaches a method for cleaning a microelectronic substrate that includes a dual damascene aperture located within an organic silicate glass material. The method uses a wet chemical etchant comprising hydrogen fluoride and hydrogen peroxide for cleaning a residue from within the dual damascene aperture while not etching the organic silicate glass material.
Further, Wu et al., in U.S. Pat. No. 6,554,002, teaches another method for cleaning a dual damascene aperture within a microelectronic structure. The method uses a solvent treatment, followed by a thermal annealing treatment and/or a sputtering treatment, for cleaning the dual damascene aperture.
Still further, Naghshineh et al., in U.S. Pat. No. 6,851,432, teaches a cleaning composition that may be used for cleaning a microelectronic structure. The cleaning composition includes an alkanolamine, a tetraalkylammonium hydroxide, a nonmetallic fluoride salt and a corrosion inhibitor.
Yet further, Peyne et al., in U.S. Pat. No. 7,157,415, teaches a post etch cleaning composition that is useful in cleaning dual damascene apertures within microelectronic structures. The cleaning composition includes in particular a choline material.
Finally, Wu et al., in U.S. Pat. No. 7,172,976, teaches yet another method for cleaning a dual damascene aperture within a microelectronic structure. The particular method uses a mild hydrogen peroxide oxidation and a subsequent etch to remove a copper oxide from a copper containing material exposed at the bottom of the dual damascene aperture, while simultaneously avoiding any copper reduction reactions involving the copper containing material.
The performance of dielectric and metal structures, such as but not limited to dual damascene structures, is likely to continue to be prominent as microelectronic technology, and in particular semiconductor technology, advances. To that end, desirable are cleaning methods and cleaning materials that efficiently assist in providing functional and reliable connections within dielectric and metal structures, such as dual damascene structures.